mirror of
https://github.com/duggasco/bc250-40cu-unlock.git
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11093c6226
The second hunk header claimed 39 new lines but the actual content has 40 (34 added + 6 context). This caused "malformed patch" errors on CachyOS kernel builds. Reported by Marcin on Discord. Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
99 lines
4.2 KiB
Diff
99 lines
4.2 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: duggasco <duggasco@gmail.com>
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Date: Mon, 18 May 2026 20:00:00 +0000
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Subject: [PATCH] drm/amdgpu/gfx10: BC-250 40 CU unlock via CC + SPI register
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writes
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Re-enable all 40 harvested CUs on the AMD BC-250 (gfx1013 / Cyan
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Skillfish / salvaged PS5 APU) by writing two hardware registers during
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CU enumeration in gfx_v10_0_get_cu_info():
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1. CC_GC_SHADER_ARRAY_CONFIG — clears the harvest enumeration mask so
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the driver, RADV, and KFD see all 40 CUs.
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2. SPI_PG_ENABLE_STATIC_WGP_MASK — enables the SPI (Shader Processor
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Input) to dispatch wavefronts to all 5 WGPs per shader array.
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Without this, CC alone changes reporting but SPI still dispatches
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to only 3 WGPs (24 CUs).
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3. RLC_PG_ALWAYS_ON_WGP_MASK — keeps all WGPs powered.
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Both CC and SPI writes are required — neither alone produces compute
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scaling. Controlled via module parameter amdgpu.bc250_cc_write_mode
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(default 0 = off, 3 = enable all). Guarded by PCI device ID 0x13FE.
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Verified: pp512 302 tok/s (24 CU) -> 466 tok/s (40 CU) = 1.54x at 2GHz.
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At 1500MHz/900mV: 230 -> 372 tok/s = 1.61x with sustainable thermals.
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4-state A/B test confirmed neither register alone has any effect:
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CC=0 SPI=0x07 (stock): 302 tok/s
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CC=0 SPI=0x1F (SPI only): 302 tok/s (no gain)
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CC=3 SPI=0x07 (CC only): 302 tok/s (no gain)
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CC=3 SPI=0x1F (both): 466 tok/s (1.54x)
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Reference: https://github.com/duggasco/bc250-40cu-unlock
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Signed-off-by: duggasco <duggasco@gmail.com>
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---
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drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 46 ++++++++++++++++++++++++
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1 file changed, 46 insertions(+)
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diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
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--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
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+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
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@@ -26,6 +26,13 @@
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#include <linux/firmware.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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+
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+/* BC-250 40 CU unlock: clears harvest mask + enables SPI dispatch to all WGPs */
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+static int bc250_cc_write_mode;
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+module_param(bc250_cc_write_mode, int, 0444);
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+MODULE_PARM_DESC(bc250_cc_write_mode,
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+ "BC-250: 0=off 1=probe-SE0SH0 2=clear-SE0SH0 3=clear-all-SAs 4=probe-all-SAs");
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+#define BC250_PCI_DEVICE_ID 0x13FE
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#include "amdgpu.h"
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#include "amdgpu_gfx.h"
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#include "amdgpu_psp.h"
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@@ -10127,6 +10134,40 @@
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amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
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mutex_lock(&adev->grbm_idx_mutex);
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+
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+ /* BC-250: unlock harvested CUs -- CC (enumeration) + SPI (dispatch) + RLC (power) */
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+ if (bc250_cc_write_mode > 0 && adev->pdev->device == BC250_PCI_DEVICE_ID) {
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+ int bc_se, bc_sh;
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+ for (bc_se = 0; bc_se < adev->gfx.config.max_shader_engines; bc_se++) {
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+ for (bc_sh = 0; bc_sh < adev->gfx.config.max_sh_per_se; bc_sh++) {
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+ u32 bc_cc_orig, bc_cc_after, bc_spi_orig, bc_spi_after;
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+ if (bc250_cc_write_mode == 2 && (bc_se > 0 || bc_sh > 0))
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+ continue;
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+ gfx_v10_0_select_se_sh(adev, bc_se, bc_sh, 0xffffffff, 0);
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+ bc_cc_orig = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
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+ WREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG, 0);
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+ bc_cc_after = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
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+ bc_spi_orig = RREG32_SOC15(GC, 0, mmSPI_PG_ENABLE_STATIC_WGP_MASK);
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+ WREG32_SOC15(GC, 0, mmSPI_PG_ENABLE_STATIC_WGP_MASK, 0x1f);
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+ bc_spi_after = RREG32_SOC15(GC, 0, mmSPI_PG_ENABLE_STATIC_WGP_MASK);
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+ WREG32_SOC15(GC, 0, mmRLC_PG_ALWAYS_ON_WGP_MASK, 0x1f);
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+ if (bc250_cc_write_mode == 1 || bc250_cc_write_mode == 4) {
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+ WREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG, bc_cc_orig);
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+ WREG32_SOC15(GC, 0, mmSPI_PG_ENABLE_STATIC_WGP_MASK, bc_spi_orig);
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+ dev_info(adev->dev,
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+ "bc250-40cu-probe: se=%d sh=%d CC=0x%08x->0x%08x SPI=0x%08x->0x%08x (restored)",
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+ bc_se, bc_sh, bc_cc_orig, bc_cc_after, bc_spi_orig, bc_spi_after);
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+ } else {
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+ dev_info(adev->dev,
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+ "bc250-40cu-enable: mode=%d se=%d sh=%d CC=0x%08x->0x%08x SPI=0x%08x->0x%08x",
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+ bc250_cc_write_mode, bc_se, bc_sh,
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+ bc_cc_orig, bc_cc_after, bc_spi_orig, bc_spi_after);
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+ }
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+ }
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+ }
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+ gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
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+ }
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+
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for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
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for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
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bitmap = i * adev->gfx.config.max_sh_per_se + j;
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--
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2.53.0
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