From fed7a6d0629cfd97e9e0db8b1bdfcd32b134f350 Mon Sep 17 00:00:00 2001 From: Deeptanshu Lal <143280861+Deeptanshuu@users.noreply.github.com> Date: Tue, 14 Jul 2026 02:58:47 +0530 Subject: [PATCH] [AGC] Decode gfx10 SOPP hint instructions (#108) * [AGC] Decode gfx10 SOPP hint instructions s_clause (0x21), s_waitcnt_depctr (0x23), s_round_mode (0x24) and s_denorm_mode (0x25) were missing from the SOPP decode table, so any shader containing one of these scheduling/mode hints failed to decode entirely with unknown-sopp. No emitter changes are needed: non-branch SOPP instructions are already emitted as no-ops. Opcodes verified against LLVM SOPInstructions.td (SOPP_Real_32_gfx10); decode and end-to-end SPIR-V compilation verified with a synthetic program containing all four hints. Co-Authored-By: Claude Fable 5 * [AGC] Narrow SOPP additions to scheduling hints only Per review: s_round_mode (0x24) and s_denorm_mode (0x25) write the shader floating-point MODE state, and the emitter's blanket SOPP no-op would have silently ignored their simm16 payloads, trading a loud decode failure for a potential floating-point semantics mismatch. They are removed and keep failing decode explicitly until their semantics are modeled or conservatively validated. s_clause (0x21) and s_waitcnt_depctr (0x23) remain: they are pure scheduler/dependency hints with no value semantics. Co-Authored-By: Claude Fable 5 --------- Co-authored-by: Claude Fable 5 --- src/SharpEmu.Libs/Agc/Gen5ShaderTranslator.cs | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/SharpEmu.Libs/Agc/Gen5ShaderTranslator.cs b/src/SharpEmu.Libs/Agc/Gen5ShaderTranslator.cs index 7337969..f044ca3 100644 --- a/src/SharpEmu.Libs/Agc/Gen5ShaderTranslator.cs +++ b/src/SharpEmu.Libs/Agc/Gen5ShaderTranslator.cs @@ -621,6 +621,8 @@ internal static class Gen5ShaderTranslator 0x10 => "SSendmsg", 0x16 => "STtraceData", 0x20 => "SInstPrefetch", + 0x21 => "SClause", + 0x23 => "SWaitcntDepctr", _ => string.Empty, };