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https://github.com/par274/sharpemu.git
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* [ShaderCompiler] Extract the backend-neutral shader compiler project Move the Gen5 (gfx10) microcode decoder, the scalar evaluator, the shader IR, and the metadata reader out of SharpEmu.Libs/Agc into a new SharpEmu.ShaderCompiler project — the half of shader compilation every codegen backend (SPIR-V today; MSL and DXIL later) consumes. Types go public: they are the contract now. Nothing in the project may depend on a host graphics API; the SPIR-V-specific artifact types (Gen5SpirvShader, Gen5SpirvStage) stay beside the emitter in Libs. Three couplings surfaced by the move, each resolved at the right depth: GuestDrawKind was defined inside VulkanVideoPresenter despite being a guest-domain, decoder-produced concept — it moves to the shared project; the evaluator's one HLE dependency (the tracked-libc-heap read fallback) becomes an injectable hook that a Libs module initializer installs before any caller can reach the evaluator; and the inline- constant table is promoted to a shared Gen5InlineConstants so backends cannot drift on constant semantics (the SPIR-V translator now delegates to it). The ShaderDump tool drops its reflection over the moved types in favor of direct typed calls; only the SPIR-V emitter, still internal to Libs until it moves to its own backend project, is reached via reflection. Verified by a clean solution build, the existing test suite, and a full ShaderDump conformance run. * [ShaderCompiler] Move the SPIR-V emitter into SharpEmu.ShaderCompiler.Vulkan Gen5SpirvTranslator (with its ALU partial), SpirvModuleBuilder, SpirvFixedShaders, and the Gen5SpirvShader/Gen5SpirvStage artifact types move whole from SharpEmu.Libs/Agc into the first per-backend codegen project. Notably it needs no Vulkan bindings reference: emitters produce bytes from the shared IR; renderers own graphics APIs. Types go public as the backend's contract; AgcExports and the presenter consume them exactly as before. The ShaderDump tool drops its last reflection: with both halves of the pipeline public it drives decode and all three emit entry points with direct typed calls, retiring the PadWithDefaults invoke shim — and it no longer references SharpEmu.Libs at all, making the conformance tool emulator-independent by design. Verified by a clean solution build, the test suite, a full ShaderDump conformance run, and a locked-mode restore under the pinned SDK. * [Gpu] Extract the guest-GPU backend seam (IGuestGpuBackend) The AGC/VideoOut/SystemService export layers now reach the renderer through IGuestGpuBackend via GuestGpu.Current (mirroring HostPlatform), instead of calling VulkanVideoPresenter statics. The Vulkan backend is a thin adapter over the existing presenter, so the extraction stays mechanical; only the adapter and the presenter itself reference the presenter now. The types crossing the seam move to Gpu/GuestGpuTypes.cs and drop their Vulkan prefixes, which an audit showed were misnomers: every field is a neutral primitive or a raw guest value (guest addresses, format and number-type codes, CB_BLEND register bitfields, verbatim sampler descriptor dwords). The one genuine Vulkan value in the old surface — the Silk.NET Format inside VulkanRenderTargetFormat, which callers never read — stops crossing: TryDecodeRenderTargetFormat is replaced at the seam by TryGetRenderTargetOutputKind, which surfaces only the Gen5PixelOutputKind callers actually consume, keeping native formats a backend-internal concern. ToVulkanSampler in AgcExports is renamed ToGuestSampler to match what it always produced. Seam rules are documented on the interface: no host-API value crosses, and submission stays coarse-grained with synchronization internal to backends. Interim exception, resolved next: shader parameters are still SPIR-V blobs. * [Gpu] Move shader compilation behind the guest-GPU backend The seam's interim exception is gone: AgcExports no longer calls Gen5SpirvTranslator or handles SPIR-V bytes. IGuestGpuBackend gains the three TryCompile entry points, which take the backend-neutral (Gen5ShaderState, Gen5ShaderEvaluation) contract plus the flat per-role resource-slot bases a multi-stage draw needs, and return opaque IGuestCompiledShader handles that only the producing backend can submit — the Vulkan backend wraps its SPIR-V in VulkanCompiledGuestShader and rejects foreign handles loudly. Draw and dispatch submissions take handles instead of byte arrays; the shader caches in AgcExports store handles. IGuestCompiledShader.Payload exposes the backend-defined compiled bytes for exactly two callers: the diagnostics dump and the size trace — documented as never-interpret. The unused _pixelSpirvCache is deleted. With this, a Metal or DX12 backend plugs in by implementing IGuestGpuBackend with its own codegen; nothing in the export layers knows which shader format exists. Verified by a clean solution build, the test suite, and a full ShaderDump conformance run under the pinned SDK. * [Gpu] Fix rename collateral from the seam extraction Address review findings: a doc comment picked up the mechanical VulkanVideoPresenter -> GuestGpu.Current rewrite and ended up naming members that do not exist on the interface, and CreateVulkanIndexBuffer kept its Vulkan prefix while every sibling factory was de-Vulkanized — it produces the neutral GuestIndexBuffer, so it is CreateGuestIndexBuffer. * [Gpu] Label diagnostics dumps with the backend's payload extension Address the review's altitude finding on DumpSpirv: the dump helper's IR-disassembly half is backend-neutral and stays put, but writing the opaque payload to a hardcoded .spv interpreted bytes the seam says never to interpret. IGuestCompiledShader now declares its payload's file extension, and the renamed DumpCompiledShader takes the handle and writes honestly-labeled dumps whichever backend produced them. * [Gpu] Make the shader-cache hit path allocation-free and lock-free Every translated draw built its cache key with a LINQ Select feeding string.Join plus one interpolated string per render target — steady per-draw allocation whether or not the shaders were already cached. The output layout is now packed exactly into a ulong (guest slot in 6 bits + output kind in 2 bits per target, host locations being the byte positions, target count in the key beside it), and the Gen5PixelOutputBinding array is only materialized on a cache miss, where compilation dwarfs it. The graphics/compute shader caches switch from Dictionary guarded by _submitTraceGate to ConcurrentDictionary, making the per-draw and per-dispatch hit paths lock-free and decoupling them from the tracing gate they coincidentally shared. And the seam-shaped render-target list is built once when a translated draw is created instead of a Select/ToArray per submission of a cached draw. * [Gpu] Replace LINQ with explicit loops in code this branch introduced Project rule going forward: no LINQ — it allocates enumerators, closures, and delegates, and this codebase is GC-pause-sensitive. The pixel-output and guest-render-target array builds and the ShaderDump store-PC collection become plain loops; pre-existing LINQ elsewhere is left for changes that already touch those lines. * [ShaderCompiler] Suppress CA2255 on the evaluator hook installer The analyzer coverage that arrived with the rebase flags ModuleInitializer in library code; this is the rule's intended advanced scenario — the hook must be installed before any code path can reach the evaluator, and every such path enters through this assembly — so suppress with that justification rather than weaken the guarantee to a static constructor's lazier timing. * [Gpu] Resolve rebase artifacts onto main Dedupe the System.Collections.Concurrent using in AgcExports that the rebase merge duplicated (main and this branch each added it), and regenerate the lock files for the new shader-compiler projects and SharpEmu.Libs against main's current package graph so --locked-mode restore matches at the branch tip. * [CI] Comment per-platform build artifact links on PRs Adds a workflow_run workflow that, after "Build and Release" finishes a pull-request build, posts (and keeps updated in place) a single PR comment linking the Windows, Linux, and macOS artifacts from that run. It runs via workflow_run rather than in the build workflow because PRs from forks build with a read-only token that cannot comment; the follow-on run executes in the base-repo context with write access and without checking out fork code. GitHub only triggers workflow_run from the default branch, so this takes effect once merged to main.
332 lines
14 KiB
C#
332 lines
14 KiB
C#
// Copyright (C) 2026 SharpEmu Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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// Synthetic-shader conformance dumper.
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//
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// Feeds hand-assembled Gen5 (gfx10) instruction words through the real
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// decode -> SPIR-V pipeline (SharpEmu.ShaderCompiler + SharpEmu.ShaderCompiler.Vulkan)
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// and writes the resulting vertex, pixel, and compute SPIR-V blobs to disk. The blobs
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// can then be checked with spirv-val / spirv-dis.
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//
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// Programs that contain buffer_store_dword automatically get a single
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// global-memory binding covering every store, which the emitter exposes as
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// guestBuffers[0] (descriptor set 0, binding 0).
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//
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// Each program carries an expectation: ExpectTranslate=true programs must
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// decode and emit the requested stages; ExpectTranslate=false programs pin a decode
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// failure that must stay loud. Any unexpected outcome makes the tool exit
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// non-zero, so it can gate scripts/CI.
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//
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// Usage: SharpEmu.Tools.ShaderDump [output-directory]
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using System.Buffers.Binary;
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using SharpEmu.HLE;
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using SharpEmu.ShaderCompiler;
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using SharpEmu.ShaderCompiler.Vulkan;
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const ulong ProgramAddress = 0x100000;
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(string Name, bool ExpectTranslate, uint[] Words)[] testPrograms =
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[
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("fmac", true, [
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0x560A0501, // v_fmac_f32 v5, v1, v2
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0x580A0501, 0x42280000, // v_fmamk_f32 v5, v1, 42.0, v2
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0x5A0A0501, 0x42280000, // v_fmaak_f32 v5, v1, v2, 42.0
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0xD52B0005, 0x00020501, // v_fmac_f32_e64 v5, v1, v2
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0xBF810000, // s_endpgm
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]),
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("muls", true, [
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0xD5690005, 0x00020501, // v_mul_lo_u32 v5, v1, v2
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0xD56A0005, 0x00020501, // v_mul_hi_u32 v5, v1, v2
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0xD56B0005, 0x00020501, // v_mul_lo_i32 v5, v1, v2
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0xD56C0005, 0x00020501, // v_mul_hi_i32 v5, v1, v2
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0xBF810000, // s_endpgm
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]),
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("mrt", true, [
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0x7E0002FF, 0x3F800000, // v_mov_b32 v0, 1.0f
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0x7E0202FF, 0x00000000, // v_mov_b32 v1, 0.0f
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0x7E0402FF, 0x00000000, // v_mov_b32 v2, 0.0f
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0x7E0602FF, 0x3F800000, // v_mov_b32 v3, 1.0f
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0x7E0802FF, 0x00000001, // v_mov_b32 v4, 1u
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0x7E0A02FF, 0x00000002, // v_mov_b32 v5, 2u
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0x7E0C02FF, 0x00000003, // v_mov_b32 v6, 3u
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0x7E0E02FF, 0x00000004, // v_mov_b32 v7, 4u
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0x7E1002FF, 0xFFFFFFFF, // v_mov_b32 v8, -1
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0x7E1202FF, 0x00000002, // v_mov_b32 v9, 2
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0x7E1402FF, 0xFFFFFFFD, // v_mov_b32 v10, -3
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0x7E1602FF, 0x00000004, // v_mov_b32 v11, 4
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0xF800000F, 0x03020100, // exp mrt0 v0, v1, v2, v3
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0xF800003F, 0x07060504, // exp mrt3 v4, v5, v6, v7
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0xF800086F, 0x0B0A0908, // exp mrt6 v8, v9, v10, v11 done
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0xBF810000, // s_endpgm
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]),
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("mrt-float2", true, [
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0x7E0002FF, 0x3F800000, // v_mov_b32 v0, 1.0f
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0x7E0202FF, 0x3E800000, // v_mov_b32 v1, 0.25f
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0x7E0402FF, 0x3E800000, // v_mov_b32 v2, 0.25f
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0x7E0602FF, 0x3F000000, // v_mov_b32 v3, 0.5f
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0xF800000F, 0x03020100, // exp mrt0 v0, v1, v2, v3
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0xF800081F, 0x03020100, // exp mrt1 v0, v1, v2, v3 done
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0xBF810000, // s_endpgm
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]),
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("mrt8", true, [
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0x7E0002FF, 0x3F800000, // v_mov_b32 v0, 1.0f
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0x7E0202FF, 0x00000000, // v_mov_b32 v1, 0.0f
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0x7E0402FF, 0x00000000, // v_mov_b32 v2, 0.0f
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0x7E0602FF, 0x3F800000, // v_mov_b32 v3, 1.0f
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0xF800000F, 0x03020100, // exp mrt0 v0, v1, v2, v3
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0xF800001F, 0x03020100, // exp mrt1 v0, v1, v2, v3
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0xF800002F, 0x03020100, // exp mrt2 v0, v1, v2, v3
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0xF800003F, 0x03020100, // exp mrt3 v0, v1, v2, v3
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0xF800004F, 0x03020100, // exp mrt4 v0, v1, v2, v3
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0xF800005F, 0x03020100, // exp mrt5 v0, v1, v2, v3
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0xF800006F, 0x03020100, // exp mrt6 v0, v1, v2, v3
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0xF800087F, 0x03020100, // exp mrt7 v0, v1, v2, v3 done
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0xBF810000, // s_endpgm
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]),
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("mrt-partial", true, [
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0x7E0002FF, 0x3F4CCCCD, // v_mov_b32 v0, 0.8f
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0x7E0202FF, 0x3F333333, // v_mov_b32 v1, 0.7f
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0xF8000803, 0x03020100, // exp mrt0 v0, v1, off, off done
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0xBF810000, // s_endpgm
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]),
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("mrt-partial-merge", true, [
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0x7E0002FF, 0x3DCCCCCD, // v_mov_b32 v0, 0.1f
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0x7E0202FF, 0x3E4CCCCD, // v_mov_b32 v1, 0.2f
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0x7E0C02FF, 0x3E99999A, // v_mov_b32 v6, 0.3f
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0x7E0E02FF, 0x3ECCCCCD, // v_mov_b32 v7, 0.4f
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0xF8000003, 0x03020100, // exp mrt0 v0, v1, off, off
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0xF800080C, 0x07060504, // exp mrt0 off, off, v6, v7 done
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0xBF810000, // s_endpgm
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]),
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("sopp-hints", true, [
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0xBFA10001, // s_clause 0x1
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0xBFA30000, // s_waitcnt_depctr 0x0
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0xBF810000, // s_endpgm
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]),
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// s_round_mode / s_denorm_mode write the FP MODE state and must keep
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// failing decode loudly until their semantics are modeled (see #108);
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// this program pins that behavior.
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("sopp-mode", false, [
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0xBFA40000, // s_round_mode 0x0
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0xBFA50000, // s_denorm_mode 0x0
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0xBF810000, // s_endpgm
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]),
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// Executable end-to-end test: compute with real ALU instructions, then
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// buffer_store_dword results to guestBuffers[0] at offsets 0/4/8, prove
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// that a store with EXEC=0 does not land (offset 12 stays sentinel), and
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// that stores work again after EXEC is restored (offset 16).
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("exec", true, [
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0xBFA10001, // s_clause 0x1 (hint no-op in an executed program, needs #108)
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0x7E0002FF, 0x3FC00000, // v_mov_b32 v0, 1.5f
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0x7E0202FF, 0x40100000, // v_mov_b32 v1, 2.25f
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0x7E0402FF, 0x41200000, // v_mov_b32 v2, 10.0f
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0x56040300, // v_fmac_f32 v2, v0, v1 -> v2 = fma(1.5, 2.25, 10.0)
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0x7E0602FF, 0x7FFFFFFF, // v_mov_b32 v3, 0x7FFFFFFF
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0x7E0802FF, 0x00010003, // v_mov_b32 v4, 0x00010003
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0xD56C0005, 0x00020903, // v_mul_hi_i32 v5, v3, v4
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0xD56B0006, 0x00020903, // v_mul_lo_i32 v6, v3, v4
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0xE0700000, 0x80020200, // buffer_store_dword v2, off, s[8:11], 0
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0xE0700004, 0x80020500, // buffer_store_dword v5, off, s[8:11], 0 offset:4
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0xE0700008, 0x80020600, // buffer_store_dword v6, off, s[8:11], 0 offset:8
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0xBEFE0380, // s_mov_b32 exec_lo, 0 -> lane inactive
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0xE070000C, 0x80020200, // buffer_store_dword v2, off, s[8:11], 0 offset:12 (masked, must not land)
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0xBEFE03C1, // s_mov_b32 exec_lo, -1 -> lane active again
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0xE0700010, 0x80020000, // buffer_store_dword v0, off, s[8:11], 0 offset:16
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0xBF810000, // s_endpgm
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]),
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];
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var outputDirectory = args.Length > 0
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? args[0]
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: Path.Combine(AppContext.BaseDirectory, "spv");
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Directory.CreateDirectory(outputDirectory);
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var failures = 0;
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foreach (var (name, expectTranslate, words) in testPrograms)
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{
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var memory = new FakeMemory();
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memory.AddRegion(ProgramAddress, words);
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var ctx = new CpuContext(memory, Generation.Gen5);
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Console.WriteLine(
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$"[{name}] decode: " +
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Gen5ShaderTranslator.Describe(ctx, ProgramAddress, ProgramAddress));
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if (!Gen5ShaderTranslator.TryDecodeProgram(ctx, ProgramAddress, out var program, out var decodeError))
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{
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if (expectTranslate)
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{
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failures++;
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Console.WriteLine($"[{name}] FAILED: decode error ({decodeError})");
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}
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else
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{
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Console.WriteLine($"[{name}] decode failed as expected ({decodeError})");
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}
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continue;
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}
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if (!expectTranslate)
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{
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failures++;
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Console.WriteLine(
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$"[{name}] FAILED: decoded successfully but is pinned as a decode failure — " +
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"if the new decode support is intentional, its semantics need verifying here first");
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continue;
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}
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// Buffer stores need a global-memory binding; the emitter resolves them by
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// instruction PC, so collect store PCs from the decoded program itself.
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var storePcs = new List<uint>();
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foreach (var instruction in program!.Instructions)
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{
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if (instruction.Opcode.StartsWith("BufferStore", StringComparison.Ordinal))
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{
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storePcs.Add(instruction.Pc);
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}
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}
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// The binding's scalar base (8 -> s[8:11]) must match the srsrc field of
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// the hand-assembled buffer_store words, and the 64-byte backing store
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// must cover every hand-assembled store offset.
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var globalBindings = storePcs.Count > 0
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? new[] { new Gen5GlobalMemoryBinding(8u, 0UL, storePcs, new byte[64]) }
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: Array.Empty<Gen5GlobalMemoryBinding>();
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var state = new Gen5ShaderState(program, new uint[16], Metadata: null);
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var evaluation = new Gen5ShaderEvaluation(
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new uint[256],
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new uint[256],
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new Dictionary<uint, IReadOnlyList<uint>>(),
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Array.Empty<Gen5ImageBinding>(),
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globalBindings);
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if (Gen5SpirvTranslator.TryCompileVertexShader(state, evaluation, out var vertexShader, out var vertexError))
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{
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var path = Path.Combine(outputDirectory, $"{name}.spv");
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File.WriteAllBytes(path, vertexShader.Spirv);
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Console.WriteLine($"[{name}] emit: success, {vertexShader.Spirv.Length} bytes -> {path}");
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}
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else
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{
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failures++;
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Console.WriteLine($"[{name}] emit: FAILED ({vertexError})");
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}
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if (Gen5SpirvTranslator.TryCompileComputeShader(state, evaluation, 1, 1, 1, out var computeShader, out var computeError))
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{
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var path = Path.Combine(outputDirectory, $"{name}-cs.spv");
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File.WriteAllBytes(path, computeShader.Spirv);
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Console.WriteLine($"[{name}] compute emit: success, {computeShader.Spirv.Length} bytes -> {path}");
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}
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else
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{
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failures++;
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Console.WriteLine($"[{name}] compute emit: FAILED ({computeError})");
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}
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if (name.StartsWith("mrt", StringComparison.Ordinal))
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{
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Gen5PixelOutputBinding[] pixelOutputs = name switch
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{
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"mrt" =>
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[
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new Gen5PixelOutputBinding(0, 0, Gen5PixelOutputKind.Float),
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new Gen5PixelOutputBinding(3, 1, Gen5PixelOutputKind.Uint),
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new Gen5PixelOutputBinding(6, 2, Gen5PixelOutputKind.Sint),
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],
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"mrt-float2" =>
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[
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new Gen5PixelOutputBinding(0, 0, Gen5PixelOutputKind.Float),
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new Gen5PixelOutputBinding(1, 1, Gen5PixelOutputKind.Float),
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],
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"mrt8" =>
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[
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new Gen5PixelOutputBinding(0, 0, Gen5PixelOutputKind.Float),
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new Gen5PixelOutputBinding(1, 1, Gen5PixelOutputKind.Float),
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new Gen5PixelOutputBinding(2, 2, Gen5PixelOutputKind.Float),
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new Gen5PixelOutputBinding(3, 3, Gen5PixelOutputKind.Float),
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new Gen5PixelOutputBinding(4, 4, Gen5PixelOutputKind.Float),
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new Gen5PixelOutputBinding(5, 5, Gen5PixelOutputKind.Float),
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new Gen5PixelOutputBinding(6, 6, Gen5PixelOutputKind.Float),
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new Gen5PixelOutputBinding(7, 7, Gen5PixelOutputKind.Float),
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],
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_ => [new Gen5PixelOutputBinding(0, 0, Gen5PixelOutputKind.Float)],
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};
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if (Gen5SpirvTranslator.TryCompilePixelShader(state, evaluation, pixelOutputs, out var pixelShader, out var pixelError))
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{
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var path = Path.Combine(outputDirectory, $"{name}-ps.spv");
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File.WriteAllBytes(path, pixelShader.Spirv);
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Console.WriteLine($"[{name}] pixel emit: success, {pixelShader.Spirv.Length} bytes -> {path}");
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}
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else
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{
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failures++;
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Console.WriteLine($"[{name}] pixel emit: FAILED ({pixelError})");
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}
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if (name == "mrt")
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{
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Gen5PixelOutputBinding[] invalidOutputs =
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[
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new Gen5PixelOutputBinding(0, 0, Gen5PixelOutputKind.Float),
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new Gen5PixelOutputBinding(3, 7, Gen5PixelOutputKind.Float),
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];
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if (Gen5SpirvTranslator.TryCompilePixelShader(state, evaluation, invalidOutputs, out _, out var invalidError))
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{
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failures++;
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Console.WriteLine("[mrt] FAILED: sparse host locations were accepted");
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}
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else
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{
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Console.WriteLine($"[mrt] sparse host locations rejected as expected ({invalidError})");
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
Console.WriteLine(failures == 0
|
|
? "RESULT: all programs behaved as expected"
|
|
: $"RESULT: {failures} unexpected outcome(s)");
|
|
Environment.ExitCode = failures == 0 ? 0 : 1;
|
|
|
|
internal sealed class FakeMemory : ICpuMemory
|
|
{
|
|
private readonly List<(ulong Base, byte[] Data)> _regions = [];
|
|
|
|
public void AddRegion(ulong baseAddress, uint[] words)
|
|
{
|
|
var bytes = new byte[words.Length * sizeof(uint)];
|
|
for (var index = 0; index < words.Length; index++)
|
|
{
|
|
BinaryPrimitives.WriteUInt32LittleEndian(
|
|
bytes.AsSpan(index * sizeof(uint)),
|
|
words[index]);
|
|
}
|
|
|
|
_regions.Add((baseAddress, bytes));
|
|
}
|
|
|
|
public bool TryRead(ulong virtualAddress, Span<byte> destination)
|
|
{
|
|
foreach (var (baseAddress, data) in _regions)
|
|
{
|
|
if (virtualAddress >= baseAddress &&
|
|
virtualAddress + (ulong)destination.Length <= baseAddress + (ulong)data.Length)
|
|
{
|
|
data.AsSpan(
|
|
(int)(virtualAddress - baseAddress),
|
|
destination.Length).CopyTo(destination);
|
|
return true;
|
|
}
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
public bool TryWrite(ulong virtualAddress, ReadOnlySpan<byte> source) => false;
|
|
}
|