[NpEntitlementAccess] added sceNpEntitlementAccessGetAddcontEntitlementInfoList export

This commit is contained in:
ParantezTech
2026-07-01 13:49:49 +03:00
parent 253d0fae3f
commit df9d0e6aaf

View File

@@ -8,6 +8,7 @@ namespace SharpEmu.Libs.Np;
public static class NpEntitlementAccessExports
{
private const int BootParamClearSize = 0x20;
private const int EmptyAddcontInfoListSize = 0x10;
[SysAbiExport(
Nid = "jO8DM8oyego",
@@ -33,6 +34,30 @@ public static class NpEntitlementAccessExports
return SetReturn(ctx, OrbisGen2Result.ORBIS_GEN2_OK);
}
[SysAbiExport(
Nid = "TFyU+KFBv54",
ExportName = "sceNpEntitlementAccessGetAddcontEntitlementInfoList",
Target = Generation.Gen4 | Generation.Gen5,
LibraryName = "libSceNpEntitlementAccess")]
public static int NpEntitlementAccessGetAddcontEntitlementInfoList(CpuContext ctx)
{
var listAddress = ctx[CpuRegister.Rsi];
if (listAddress != 0)
{
Span<byte> emptyList = stackalloc byte[EmptyAddcontInfoListSize];
emptyList.Clear();
if (!ctx.Memory.TryWrite(listAddress, emptyList))
{
return SetReturn(ctx, OrbisGen2Result.ORBIS_GEN2_ERROR_MEMORY_FAULT);
}
}
TraceNpEntitlementAccess(
$"get_addcont_info_list service=0x{ctx[CpuRegister.Rdi]:X16} list=0x{listAddress:X16} " +
$"max={ctx[CpuRegister.Rdx]} flags=0x{ctx[CpuRegister.Rcx]:X16} -> empty");
return SetReturn(ctx, OrbisGen2Result.ORBIS_GEN2_OK);
}
private static int SetReturn(CpuContext ctx, OrbisGen2Result result)
{
ctx[CpuRegister.Rax] = unchecked((ulong)(int)result);