config: enable NFT_QUEUE and NFT_TUNNEL

thanks to cow for testing. legend as usual.

.config

@@ -1408,8 +1408,8 @@ CONFIG_NFT_LIMIT=m
 CONFIG_NFT_MASQ=m
 CONFIG_NFT_REDIR=m
 CONFIG_NFT_NAT=m
-# CONFIG_NFT_TUNNEL is not set
-# CONFIG_NFT_QUEUE is not set
+CONFIG_NFT_TUNNEL=m
+CONFIG_NFT_QUEUE=m
 # CONFIG_NFT_QUOTA is not set
 CONFIG_NFT_REJECT=m
 CONFIG_NFT_REJECT_INET=m
@@ -2015,6 +2015,7 @@ CONFIG_PNPACPI=y
 CONFIG_BLK_DEV=y
 # CONFIG_BLK_DEV_NULL_BLK is not set
 # CONFIG_BLK_DEV_FD is not set
+CONFIG_CDROM=y
 # CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set
 CONFIG_ZRAM=m
 CONFIG_ZRAM_BACKEND_LZ4=y
@@ -2132,7 +2133,7 @@ CONFIG_SCSI_PROC_FS=y
 #
 CONFIG_BLK_DEV_SD=y
 # CONFIG_CHR_DEV_ST is not set
-# CONFIG_BLK_DEV_SR is not set
+CONFIG_BLK_DEV_SR=y
 CONFIG_CHR_DEV_SG=y
 CONFIG_BLK_DEV_BSG=y
 # CONFIG_CHR_DEV_SCH is not set
@@ -2155,7 +2156,102 @@ CONFIG_SCSI_SCAN_ASYNC=y
 # CONFIG_SCSI_DH is not set
 # end of SCSI device support
 
-# CONFIG_ATA is not set
+CONFIG_ATA=y
+CONFIG_SATA_HOST=y
+CONFIG_PATA_TIMINGS=y
+CONFIG_ATA_VERBOSE_ERROR=y
+CONFIG_ATA_FORCE=y
+CONFIG_ATA_ACPI=y
+# CONFIG_SATA_ZPODD is not set
+CONFIG_SATA_PMP=y
+
+#
+# Controllers with non-SFF native interface
+#
+# CONFIG_SATA_AHCI is not set
+# CONFIG_SATA_AHCI_PLATFORM is not set
+# CONFIG_AHCI_DWC is not set
+CONFIG_AHCI_SALINA=m
+# CONFIG_SATA_INIC162X is not set
+# CONFIG_SATA_ACARD_AHCI is not set
+# CONFIG_SATA_SIL24 is not set
+CONFIG_ATA_SFF=y
+
+#
+# SFF controllers with custom DMA interface
+#
+# CONFIG_PDC_ADMA is not set
+# CONFIG_SATA_QSTOR is not set
+# CONFIG_SATA_SX4 is not set
+CONFIG_ATA_BMDMA=y
+
+#
+# SATA SFF controllers with BMDMA
+#
+# CONFIG_ATA_PIIX is not set
+# CONFIG_SATA_DWC is not set
+# CONFIG_SATA_MV is not set
+# CONFIG_SATA_NV is not set
+# CONFIG_SATA_PROMISE is not set
+# CONFIG_SATA_SIL is not set
+# CONFIG_SATA_SIS is not set
+# CONFIG_SATA_SVW is not set
+# CONFIG_SATA_ULI is not set
+# CONFIG_SATA_VIA is not set
+# CONFIG_SATA_VITESSE is not set
+
+#
+# PATA SFF controllers with BMDMA
+#
+# CONFIG_PATA_ALI is not set
+# CONFIG_PATA_AMD is not set
+# CONFIG_PATA_ARTOP is not set
+# CONFIG_PATA_ATIIXP is not set
+# CONFIG_PATA_ATP867X is not set
+# CONFIG_PATA_CMD64X is not set
+# CONFIG_PATA_CYPRESS is not set
+# CONFIG_PATA_EFAR is not set
+# CONFIG_PATA_HPT366 is not set
+# CONFIG_PATA_HPT37X is not set
+# CONFIG_PATA_HPT3X2N is not set
+# CONFIG_PATA_HPT3X3 is not set
+# CONFIG_PATA_IT8213 is not set
+# CONFIG_PATA_IT821X is not set
+# CONFIG_PATA_JMICRON is not set
+# CONFIG_PATA_MARVELL is not set
+# CONFIG_PATA_NETCELL is not set
+# CONFIG_PATA_NINJA32 is not set
+# CONFIG_PATA_NS87415 is not set
+# CONFIG_PATA_OLDPIIX is not set
+# CONFIG_PATA_OPTIDMA is not set
+# CONFIG_PATA_PDC2027X is not set
+# CONFIG_PATA_PDC_OLD is not set
+# CONFIG_PATA_RADISYS is not set
+# CONFIG_PATA_RDC is not set
+# CONFIG_PATA_SCH is not set
+# CONFIG_PATA_SERVERWORKS is not set
+# CONFIG_PATA_SIL680 is not set
+# CONFIG_PATA_SIS is not set
+# CONFIG_PATA_TOSHIBA is not set
+# CONFIG_PATA_TRIFLEX is not set
+# CONFIG_PATA_VIA is not set
+# CONFIG_PATA_WINBOND is not set
+
+#
+# PIO-only SFF controllers
+#
+# CONFIG_PATA_CMD640_PCI is not set
+# CONFIG_PATA_MPIIX is not set
+# CONFIG_PATA_NS87410 is not set
+# CONFIG_PATA_OPTI is not set
+# CONFIG_PATA_RZ1000 is not set
+
+#
+# Generic fallback / legacy drivers
+#
+# CONFIG_PATA_ACPI is not set
+# CONFIG_ATA_GENERIC is not set
+# CONFIG_PATA_LEGACY is not set
 CONFIG_MD=y
 CONFIG_BLK_DEV_MD=y
 CONFIG_MD_BITMAP=y
@@ -3025,6 +3121,7 @@ CONFIG_SENSORS_K10TEMP=m
 # CONFIG_SENSORS_CHIPCAP2 is not set
 # CONFIG_SENSORS_CORSAIR_CPRO is not set
 # CONFIG_SENSORS_CORSAIR_PSU is not set
+# CONFIG_SENSORS_DRIVETEMP is not set
 # CONFIG_SENSORS_DS620 is not set
 # CONFIG_SENSORS_DS1621 is not set
 # CONFIG_SENSORS_DELL_SMM is not set
@@ -4176,6 +4273,7 @@ CONFIG_LEDS_CLASS_MULTICOLOR=m
 CONFIG_LEDS_TRIGGERS=y
 # CONFIG_LEDS_TRIGGER_TIMER is not set
 # CONFIG_LEDS_TRIGGER_ONESHOT is not set
+# CONFIG_LEDS_TRIGGER_DISK is not set
 # CONFIG_LEDS_TRIGGER_HEARTBEAT is not set
 # CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
 # CONFIG_LEDS_TRIGGER_CPU is not set

linux.patch

@@ -468,6 +468,628 @@ index 53fbd2e0acdd..d36c1909e0e6 100644
  obj-$(CONFIG_S390)		+= s390/
 +
 +obj-$(CONFIG_X86_PS5)		+= ps5/
+diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
+index 2349bca136e0..3efbb88fdc32 100644
+--- a/drivers/ata/Kconfig
++++ b/drivers/ata/Kconfig
+@@ -299,6 +299,18 @@ config AHCI_QORIQ
+ 
+ 	  If unsure, say N.
+ 
++config AHCI_SALINA
++	tristate "Sony PlayStation 5 Salina SATA / BD-ROM AHCI support"
++	depends on PCI
++	depends on X86_PS5 || COMPILE_TEST
++	select SATA_HOST
++	help
++	  This option enables support for the PlayStation 5 "Salina" SATA
++	  AHCI controller (PCI 104d:9105 / 104d:9106) that fronts the
++	  internal Blu-ray drive.
++
++	  If unsure, say N.
++
+ config SATA_FSL
+ 	tristate "Freescale 3.0Gbps SATA support"
+ 	depends on FSL_SOC || COMPILE_TEST
+diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
+index 20e6645ab737..bc98a92325b7 100644
+--- a/drivers/ata/Makefile
++++ b/drivers/ata/Makefile
+@@ -27,6 +27,8 @@ obj-$(CONFIG_AHCI_ST)		+= ahci_st.o libahci.o libahci_platform.o
+ obj-$(CONFIG_AHCI_TEGRA)	+= ahci_tegra.o libahci.o libahci_platform.o
+ obj-$(CONFIG_AHCI_XGENE)	+= ahci_xgene.o libahci.o libahci_platform.o
+ obj-$(CONFIG_AHCI_QORIQ)	+= ahci_qoriq.o libahci.o libahci_platform.o
++obj-$(CONFIG_AHCI_SALINA)	+= ahci_salina_drv.o libahci.o
++ahci_salina_drv-y		:= ahci_salina.o ahci_salina_phy.o
+ 
+ # SFF w/ custom DMA
+ obj-$(CONFIG_PDC_ADMA)		+= pdc_adma.o
+diff --git a/drivers/ata/ahci_salina.c b/drivers/ata/ahci_salina.c
+new file mode 100644
+index 000000000000..c020194eb44a
+--- /dev/null
++++ b/drivers/ata/ahci_salina.c
+@@ -0,0 +1,340 @@
++// SPDX-License-Identifier: GPL-2.0-only
++/*
++ * PlayStation 5 Salina SATA / BD-ROM AHCI host driver
++ *
++ */
++
++#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
++
++#include <linux/module.h>
++#include <linux/pci.h>
++#include <linux/io.h>
++#include <linux/dma-mapping.h>
++#include <linux/pm.h>
++#include <linux/libata.h>
++#include <linux/ps5.h>
++#include <scsi/scsi_host.h>
++
++#include "ahci.h"
++#include "ahci_salina_phy.h"
++
++#define PCI_DEVICE_ID_SPCIE	0x9107
++
++#define SALINA_ICC_DEV_BD	0x01
++
++struct salina_ahci {
++	struct salina_sata_phy	phy;
++	struct pci_dev		*glue;
++};
++
++static int salina_glue_map(struct salina_ahci *sa)
++{
++	struct pci_dev *glue;
++
++	glue = pci_get_device(PCI_VENDOR_ID_SONY, PCI_DEVICE_ID_SPCIE, NULL);
++	if (!glue)
++		return -ENODEV;
++
++	if (!(pci_resource_flags(glue, 2) & IORESOURCE_MEM) ||
++	    !(pci_resource_flags(glue, 4) & IORESOURCE_MEM)) {
++		pci_dev_put(glue);
++		return -ENODEV;
++	}
++
++	sa->phy.glue_phy = ioremap(pci_resource_start(glue, 2),
++				   pci_resource_len(glue, 2));
++	if (!sa->phy.glue_phy) {
++		pci_dev_put(glue);
++		return -ENOMEM;
++	}
++
++	sa->phy.glue_pcs = ioremap(pci_resource_start(glue, 4),
++				   pci_resource_len(glue, 4));
++	if (!sa->phy.glue_pcs) {
++		iounmap(sa->phy.glue_phy);
++		sa->phy.glue_phy = NULL;
++		pci_dev_put(glue);
++		return -ENOMEM;
++	}
++
++	sa->glue = glue;
++	return 0;
++}
++
++static void salina_glue_unmap(struct salina_ahci *sa)
++{
++	if (sa->phy.glue_pcs) {
++		iounmap(sa->phy.glue_pcs);
++		sa->phy.glue_pcs = NULL;
++	}
++	if (sa->phy.glue_phy) {
++		iounmap(sa->phy.glue_phy);
++		sa->phy.glue_phy = NULL;
++	}
++	if (sa->glue) {
++		pci_dev_put(sa->glue);
++		sa->glue = NULL;
++	}
++}
++
++static int salina_pick_bar(u16 devid, u32 chip_id, unsigned int *abar,
++			   u32 *port_off)
++{
++	bool is_9106 = (devid == PCI_DEVICE_ID_AHCI_B);
++
++	if (!is_9106 && chip_id == SALINA_CHIP_SALINA2)
++		return -ENODEV;
++
++	*abar = 0;
++	*port_off = is_9106 ? 0x2000 : 0;
++	return 0;
++}
++
++static struct ata_port_operations salina_ahci_ops = {
++	.inherits = &ahci_ops,
++};
++
++static const struct ata_port_info salina_port_info = {
++	.flags		= AHCI_FLAG_COMMON,
++	.pio_mask	= ATA_PIO4,
++	.udma_mask	= ATA_UDMA6,
++	.port_ops	= &salina_ahci_ops,
++};
++
++static const struct scsi_host_template salina_ahci_sht = {
++	AHCI_SHT(KBUILD_MODNAME),
++};
++
++static int salina_ahci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
++{
++	struct device *dev = &pdev->dev;
++	const struct ata_port_info *ppi[] = { &salina_port_info, NULL };
++	struct ahci_host_priv *hpriv;
++	struct ata_host *host;
++	struct salina_ahci *sa;
++	unsigned int abar, n_ports;
++	u32 chip_id;
++	u8 state;
++	int rc;
++
++	if (!spcie_is_initialized()) {
++		dev_warn(dev, "spcie not initialized yet, deferring\n");
++		return -EPROBE_DEFER;
++	}
++
++	rc = pcim_enable_device(pdev);
++	if (rc)
++		return rc;
++
++	pci_set_master(pdev);
++
++	rc = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
++	if (rc)
++		return rc;
++
++	sa = devm_kzalloc(dev, sizeof(*sa), GFP_KERNEL);
++	if (!sa)
++		return -ENOMEM;
++
++	rc = salina_glue_map(sa);
++	if (rc) {
++		dev_err(dev, "glue (104d:9107) map failed: %d\n", rc);
++		return rc;
++	}
++
++	chip_id = spcie_get_chip_id();
++	if (chip_id != SALINA_CHIP_SALINA && chip_id != SALINA_CHIP_SALINA2) {
++		dev_err(dev, "unknown Salina chip id %#x\n", chip_id);
++		rc = -ENODEV;
++		goto err_glue;
++	}
++
++	rc = salina_pick_bar(pdev->device, chip_id, &abar, &sa->phy.port_off);
++	if (rc) {
++		dev_info(dev, "SALINA2 SATA0 dummy device, claiming but not attaching\n");
++		pci_set_drvdata(pdev, NULL);
++		salina_glue_unmap(sa);
++		return 0;
++	}
++
++	rc = pcim_iomap_regions(pdev, BIT(abar), KBUILD_MODNAME);
++	if (rc)
++		goto err_glue;
++
++	sa->phy.ctrl		= pcim_iomap_table(pdev)[abar];
++	sa->phy.chip_id		= chip_id;
++	sa->phy.devid		= (pdev->device << 16) | pdev->vendor;
++	sa->phy.is_bd		= true;
++	sa->phy.rx_tracelen	= 0xff;
++	sa->phy.tx_tracelen	= 0xff;
++
++	icc_device_power_get(SALINA_ICC_DEV_BD, &state);
++	if (state != 1)
++		icc_device_power_control(SALINA_ICC_DEV_BD, 1);
++
++	rc = salina_sata_phy_init(&sa->phy);
++	if (rc) {
++		dev_err(dev, "Salina SATA PHY init failed: %d\n", rc);
++		goto err_glue;
++	}
++
++	hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
++	if (!hpriv) {
++		rc = -ENOMEM;
++		goto err_glue;
++	}
++
++	hpriv->mmio = sa->phy.ctrl + sa->phy.port_off;
++	hpriv->plat_data = sa;
++	hpriv->flags = AHCI_HFLAG_NO_PMP;
++
++	ahci_save_initial_config(dev, hpriv);
++
++	rc = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI | PCI_IRQ_INTX);
++	if (rc < 0) {
++		dev_err(dev, "irq alloc failed: %d\n", rc);
++		goto err_glue;
++	}
++	hpriv->irq = pci_irq_vector(pdev, 0);
++
++	n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
++
++	host = ata_host_alloc_pinfo(dev, ppi, n_ports);
++	if (!host) {
++		rc = -ENOMEM;
++		goto err_glue;
++	}
++	host->private_data = hpriv;
++
++	if (!(hpriv->cap & HOST_CAP_SSS))
++		host->flags |= ATA_HOST_PARALLEL_SCAN;
++
++	rc = ahci_reset_controller(host);
++	if (rc)
++		goto err_glue;
++
++	ahci_init_controller(host);
++	ahci_print_info(host, "Salina");
++
++	pci_set_drvdata(pdev, host);
++
++	dev_info(dev,
++		 "Salina SATA up (chip %#x, devid %#x, BAR%u, port_off %#x, %u ports)\n",
++		 sa->phy.chip_id, sa->phy.devid, abar, sa->phy.port_off, n_ports);
++
++	return ahci_host_activate(host, &salina_ahci_sht);
++
++err_glue:
++	salina_glue_unmap(sa);
++	return rc;
++}
++
++static void salina_ahci_remove(struct pci_dev *pdev)
++{
++	struct ata_host *host = pci_get_drvdata(pdev);
++	struct ahci_host_priv *hpriv;
++	struct salina_ahci *sa;
++
++	if (!host)
++		return;
++
++	hpriv = host->private_data;
++	sa = hpriv->plat_data;
++
++	ata_host_detach(host);
++	pci_free_irq_vectors(pdev);
++	salina_glue_unmap(sa);
++}
++
++#ifdef CONFIG_PM_SLEEP
++static int salina_ahci_suspend(struct device *dev)
++{
++	struct pci_dev *pdev = to_pci_dev(dev);
++	struct ata_host *host = pci_get_drvdata(pdev);
++	struct ahci_host_priv *hpriv;
++	void __iomem *mmio;
++	u32 ctl;
++	int rc;
++
++	if (!host)
++		return 0;
++
++	hpriv = host->private_data;
++	mmio = hpriv->mmio;
++
++	ctl = readl(mmio + HOST_CTL);
++	ctl &= ~HOST_IRQ_EN;
++	writel(ctl, mmio + HOST_CTL);
++	readl(mmio + HOST_CTL);
++
++	rc = ata_host_suspend(host, PMSG_SUSPEND);
++	if (rc)
++		return rc;
++
++	pci_save_state(pdev);
++	pci_set_power_state(pdev, PCI_D3hot);
++	return 0;
++}
++
++static int salina_ahci_resume(struct device *dev)
++{
++	struct pci_dev *pdev = to_pci_dev(dev);
++	struct ata_host *host = pci_get_drvdata(pdev);
++	struct ahci_host_priv *hpriv;
++	struct salina_ahci *sa;
++	int rc;
++
++	if (!host)
++		return 0;
++
++	hpriv = host->private_data;
++	sa = hpriv->plat_data;
++
++	rc = pci_set_power_state(pdev, PCI_D0);
++	if (rc)
++		return rc;
++	pci_restore_state(pdev);
++	pci_set_master(pdev);
++
++	rc = salina_sata_phy_init(&sa->phy);
++	if (rc) {
++		dev_err(dev, "PHY re-init on resume failed: %d\n", rc);
++		return rc;
++	}
++
++	rc = ahci_reset_controller(host);
++	if (rc)
++		return rc;
++
++	ahci_init_controller(host);
++	ata_host_resume(host);
++
++	return 0;
++}
++#endif
++
++static SIMPLE_DEV_PM_OPS(salina_ahci_pm, salina_ahci_suspend, salina_ahci_resume);
++
++static const struct pci_device_id salina_ahci_tbl[] = {
++	{ PCI_DEVICE(PCI_VENDOR_ID_SONY, PCI_DEVICE_ID_AHCI_A) },
++	{ PCI_DEVICE(PCI_VENDOR_ID_SONY, PCI_DEVICE_ID_AHCI_B) },
++	{ }
++};
++MODULE_DEVICE_TABLE(pci, salina_ahci_tbl);
++
++static struct pci_driver salina_ahci_driver = {
++	.name		= KBUILD_MODNAME,
++	.id_table	= salina_ahci_tbl,
++	.probe		= salina_ahci_probe,
++	.remove		= salina_ahci_remove,
++	.driver		= {
++		.pm = &salina_ahci_pm,
++	},
++};
++
++module_pci_driver(salina_ahci_driver);
++
++MODULE_AUTHOR("Armandas Kvietkus");
++MODULE_DESCRIPTION("PlayStation 5 Salina SATA / BD-ROM AHCI driver");
++MODULE_LICENSE("GPL");
++MODULE_SOFTDEP("pre: libahci spcie");
+diff --git a/drivers/ata/ahci_salina_phy.c b/drivers/ata/ahci_salina_phy.c
+new file mode 100644
+index 000000000000..c5e85ae102ea
+--- /dev/null
++++ b/drivers/ata/ahci_salina_phy.c
+@@ -0,0 +1,183 @@
++// SPDX-License-Identifier: GPL-2.0-only
++#include <linux/kernel.h>
++#include <linux/delay.h>
++#include <linux/device.h>
++#include "ahci_salina_phy.h"
++
++static inline u32 phy_rd(struct salina_sata_phy *p, u32 off)
++{
++	return readl(p->ctrl + off);
++}
++
++static inline void phy_wr(struct salina_sata_phy *p, u32 off, u32 val)
++{
++	writel(val, p->ctrl + off);
++}
++
++static inline void phy_rmw(struct salina_sata_phy *p, u32 off, u32 keep, u32 set)
++{
++	phy_wr(p, off, (phy_rd(p, off) & keep) | set);
++}
++
++static inline u32 port_rd(struct salina_sata_phy *p, u32 off)
++{
++	return readl(p->ctrl + p->port_off + off);
++}
++
++static inline void port_wr(struct salina_sata_phy *p, u32 off, u32 val)
++{
++	writel(val, p->ctrl + p->port_off + off);
++}
++
++static inline void lane_sel(struct salina_sata_phy *p, u32 sel, u32 val)
++{
++	writel(val, p->glue_phy + SALINA_GLUE_PHY_BASE + sel);
++}
++
++static inline u32 efuse_rd(struct salina_sata_phy *p, u32 off)
++{
++	return readl(p->glue_pcs + SALINA_GLUE_PCS_BASE + off);
++}
++
++static u32 trace_len(struct salina_sata_phy *p, u32 raw)
++{
++	u32 def = p->is_bd ? 10 : 4;
++
++	if (raw == 0 || raw > 0xfe)
++		return def;
++	return (raw >> 5 & 7) + (raw & 0x1f);
++}
++
++int salina_sata_phy_init(struct salina_sata_phy *p)
++{
++	u32 trim[6];
++	u32 efuse, valid, sel, lane;
++	u32 rx, tx;
++	u32 a, b, c, d, e, f, rc;
++	bool tx_hi;
++
++	sel = (p->devid != SALINA_DEVID_A) ? SALINA_PHY_SEL_B : SALINA_PHY_SEL_A;
++	lane_sel(p, sel, 2);
++	lane_sel(p, sel, 3);
++	lane_sel(p, sel, 1);
++
++	efuse = efuse_rd(p, SALINA_EFUSE_TRIM);
++	valid = efuse_rd(p, SALINA_EFUSE_VALID);
++
++	trim[0] = trim[1] = trim[2] = trim[3] = 0x10;
++	trim[4] = trim[5] = 0x28;
++
++	if (valid & SALINA_EFUSE_VALID_A) {
++		trim[4] = efuse & 0x3f;
++		trim[2] = efuse >> 6 & 0x1f;
++		trim[0] = efuse >> 0xb & 0x1f;
++	}
++	if (valid & SALINA_EFUSE_VALID_B) {
++		trim[5] = efuse >> 0x10 & 0x3f;
++		trim[3] = efuse >> 0x16 & 0x1f;
++		trim[1] = efuse >> 0x1b;
++	}
++
++	lane = (p->devid != SALINA_DEVID_A) ? 1 : 0;
++
++	phy_rmw(p, 0xa0, 0xfbff03ff, (trim[lane + 4] << 10) | 0x4000000);
++	phy_rmw(p, 0x14, ~0u, 0x100000);
++	phy_rmw(p, 0x54, 0xfffff07f, trim[lane + 2] << 7);
++	phy_rmw(p, 0x1c, ~0u, 4);
++	phy_rmw(p, 0x78, 0xfffffe0f, trim[lane] << 4);
++
++	rx = trace_len(p, p->rx_tracelen);
++	tx = trace_len(p, p->tx_tracelen);
++
++	tx_hi = tx > 5;
++	if (tx_hi) {
++		c = 0x2000;
++		if (tx < 9) {
++			b = 0x1000000;
++			a = 0x200000;
++		} else {
++			a = (tx <= 0xc) ? 0x230000 : 0x260000;
++			b = (tx > 0xc) ? 0x9000000 : 0x5000000;
++		}
++	} else {
++		b = 0;
++		a = (tx >= 3) ? 0x1e0000 : 0x1d0000;
++		c = (tx < 3) ? 0x4000 : 0x2000;
++	}
++
++	e = (tx > 8) ? 0x4000 : 0;
++	f = (tx > 8) ? 0x80 : 0;
++	d = e | 0x12000;
++	rc = f | 0x900;
++	e += 0x6000;
++	f += 0x8c0;
++	if (tx < 6) {
++		u32 ge3 = (tx >= 3) ? 1 : 0;
++
++		d = ge3 * 0x1000 + 0xd000;
++		rc = (ge3 * 0x40) | 0x880;
++		e = ge3 << 0xd;
++		f = ge3 * 0x40 + 0x800;
++	}
++
++	phy_rmw(p, 0x4c, 0xffc0ffff, a);
++	phy_rmw(p, 0x4c, 0xc0ffffff, b);
++	phy_rmw(p, 0x54, 0xffff9fff, c);
++	phy_rmw(p, 0x7c, 0xfffff03f, f);
++	phy_rmw(p, 0x7c, 0xfffc0fff, e);
++	phy_rmw(p, 0x5c, 0x0fffffff, (tx < 3) ? 0x60000000 : 0x50000000);
++	phy_rmw(p, 0x80, 0xfffff03f, rc);
++	phy_rmw(p, 0x80, 0xfffc0fff, d);
++	phy_rmw(p, 0x4c, 0xfffffff0, tx_hi ? 5 : 3);
++
++	{
++		u32 rx_coef, rx_amp, rx_eq;
++
++		if (rx < 3) {
++			rx_coef = 0x100;
++			rx_amp = 0x40;
++			rx_eq = 2;
++		} else if (rx < 6) {
++			rx_coef = 0x100;
++			rx_amp = 0x50;
++			rx_eq = 3;
++		} else {
++			rx_amp = 0x60;
++			rx_coef = 0x200;
++			rx_eq = 5;
++		}
++		phy_rmw(p, 0x6c, 0xfffff0ff, rx_coef);
++		phy_rmw(p, 0x84, 0xffffff00, rx_amp | rx_eq);
++	}
++
++	phy_rmw(p, 0x40, 0xffffffe0, 0x12);
++	phy_rmw(p, 0x40, 0xffffc0ff, 0x3100);
++	phy_rmw(p, 0x40, 0xffe0ffff, 0xe0000);
++	phy_rmw(p, 0x40, 0xffffff1f, 0x80);
++	phy_rmw(p, 0x3c, 0x1fffefff, 0xa0000000);
++	phy_rmw(p, 0x44, 0xffffef80, 0x23);
++	phy_rmw(p, 0x1c, 0xff0fffff, 0x200000);
++	phy_rmw(p, 0xdc, 0xffffe0ff, 0x400);
++	phy_rmw(p, 0x24, ~0u, 0x30);
++
++	lane_sel(p, sel, 0);
++
++	{
++		int i;
++
++		for (i = 0; i < 100; i++) {
++			if (port_rd(p, SALINA_PHY_RDY_REG) & SALINA_PHY_RDY)
++				break;
++			udelay(10);
++		}
++		if (i == 100)
++			return -ETIMEDOUT;
++	}
++
++	port_wr(p, 0, port_rd(p, 0) & 0xe7ffffff);
++	port_wr(p, 0xc, 1);
++	port_wr(p, 0xb8, port_rd(p, 0xb8) | 0x20000);
++	port_wr(p, 0x118, (port_rd(p, 0x118) & 0xffe3ffff) | 0x40000);
++
++	return 0;
++}
+diff --git a/drivers/ata/ahci_salina_phy.h b/drivers/ata/ahci_salina_phy.h
+new file mode 100644
+index 000000000000..39cc76f39e06
+--- /dev/null
++++ b/drivers/ata/ahci_salina_phy.h
+@@ -0,0 +1,45 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++#ifndef _SALINA_SATA_PHY_H
++#define _SALINA_SATA_PHY_H
++
++#include <linux/types.h>
++#include <linux/io.h>
++
++#define PCI_DEVICE_ID_AHCI_A	0x9105
++#define PCI_DEVICE_ID_AHCI_B	0x9106
++
++#define SALINA_DEVID_A		0x9105104d
++#define SALINA_DEVID_B		0x9106104d
++
++#define SALINA_CHIP_SALINA	0x110000
++#define SALINA_CHIP_SALINA2	0x120000
++
++#define SALINA_GLUE_PHY_BASE	0x180000
++#define SALINA_GLUE_PCS_BASE	0x4000
++
++#define SALINA_EFUSE_TRIM	0x48
++#define SALINA_EFUSE_VALID	0x6c
++#define SALINA_EFUSE_VALID_A	0x40000
++#define SALINA_EFUSE_VALID_B	0x4000000
++
++#define SALINA_PHY_SEL_A	0x2c
++#define SALINA_PHY_SEL_B	0x30
++
++#define SALINA_PHY_RDY		BIT(0)
++#define SALINA_PHY_RDY_REG	0xdc
++
++struct salina_sata_phy {
++	void __iomem	*ctrl;
++	void __iomem	*glue_phy;
++	void __iomem	*glue_pcs;
++	u32		port_off;
++	u32		chip_id;
++	u32		devid;
++	u32		rx_tracelen;
++	u32		tx_tracelen;
++	bool		is_bd;
++};
++
++int salina_sata_phy_init(struct salina_sata_phy *p);
++
++#endif
 diff --git a/drivers/firmware/dmi-id.c b/drivers/firmware/dmi-id.c
 index 477a37e2ef80..e1af70946c89 100644
 --- a/drivers/firmware/dmi-id.c
@@ -706,7 +1328,7 @@ index 321310ba2c08..764da52902ac 100644
  	header = (const struct common_firmware_header *)
  		adev->sdma.instance[instance].fw->data;
 diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
-index 8b60299b73ef..db803401a3be 100644
+index 8b60299b73ef..0a3ad54066d6 100644
 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
 +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
 @@ -4202,6 +4202,14 @@ static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
@@ -784,6 +1406,77 @@ index 8b60299b73ef..db803401a3be 100644
  		amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2);
  		amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2_JT);
  	} else {
+@@ -10104,6 +10130,24 @@ static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev)
+ 	return cu_active_bitmap;
+ }
+ 
++/* PS5 harvested-CU unlock.
++ *   0 = disabled
++ *   1 = probe only (write then restore, log values)
++ *   2 = unlock SE0/SH0 only
++ *   3 = unlock all SE/SH (default)
++ *   4 = probe only, all SE/SH
++ * Override on the kernel command line, e.g.:
++ *   amdgpu.ps5_cu_unlock=0   (disable)
++ *   amdgpu.ps5_cu_unlock=1   (probe)
++ */
++static int ps5_cu_unlock = 3;
++module_param(ps5_cu_unlock, int, 0444);
++MODULE_PARM_DESC(ps5_cu_unlock,
++	"PS5 harvested-CU unlock (0=off, 1=probe, 2=SE0/SH0, 3=all (default), 4=probe-all)");
++
++// PCI device ID of the silicon this unlock applies to.
++#define PS5_PCI_DEVID_RETAIL 0x13FB
++
+ static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
+ 				 struct amdgpu_cu_info *cu_info)
+ {
+@@ -10117,6 +10161,45 @@ static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
+ 	amdgpu_gfx_parse_disable_cu(adev, disable_masks, 4, 2);
+ 
+ 	mutex_lock(&adev->grbm_idx_mutex);
++	/* PS5: unlock harvested CUs. CC alone updates enumeration but SPI
++	 * still dispatches only to enabled WGPs; both writes are required
++	 * (verified empirically on BC-250). */
++	if (ps5_cu_unlock > 0 &&
++	    adev->pdev->vendor == PCI_VENDOR_ID_ATI &&
++	    adev->pdev->device == PS5_PCI_DEVID_RETAIL) {
++		int ps5_se, ps5_sh;
++		for (ps5_se = 0; ps5_se < adev->gfx.config.max_shader_engines; ps5_se++) {
++			for (ps5_sh = 0; ps5_sh < adev->gfx.config.max_sh_per_se; ps5_sh++) {
++				u32 ps5_cc_orig, ps5_cc_after, ps5_spi_orig, ps5_spi_after;
++				if (ps5_cu_unlock == 2 && (ps5_se > 0 || ps5_sh > 0))
++					continue;
++				gfx_v10_0_select_se_sh(adev, ps5_se, ps5_sh, 0xffffffff, 0);
++				ps5_cc_orig = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
++				WREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG, 0);
++				ps5_cc_after = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
++				ps5_spi_orig = RREG32_SOC15(GC, 0, mmSPI_PG_ENABLE_STATIC_WGP_MASK);
++				WREG32_SOC15(GC, 0, mmSPI_PG_ENABLE_STATIC_WGP_MASK, 0x1f);
++				ps5_spi_after = RREG32_SOC15(GC, 0, mmSPI_PG_ENABLE_STATIC_WGP_MASK);
++				WREG32_SOC15(GC, 0, mmRLC_PG_ALWAYS_ON_WGP_MASK, 0x1f);
++				if (ps5_cu_unlock == 1 || ps5_cu_unlock == 4) {
++					WREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG, ps5_cc_orig);
++					WREG32_SOC15(GC, 0, mmSPI_PG_ENABLE_STATIC_WGP_MASK, ps5_spi_orig);
++					dev_info(adev->dev,
++						"ps5-40cu-probe: se=%d sh=%d CC=0x%08x->0x%08x SPI=0x%08x->0x%08x (restored)",
++						ps5_se, ps5_sh,
++						ps5_cc_orig, ps5_cc_after,
++						ps5_spi_orig, ps5_spi_after);
++				} else {
++					dev_info(adev->dev,
++						"ps5-40cu-enable: mode=%d se=%d sh=%d CC=0x%08x->0x%08x SPI=0x%08x->0x%08x",
++						ps5_cu_unlock, ps5_se, ps5_sh,
++						ps5_cc_orig, ps5_cc_after,
++						ps5_spi_orig, ps5_spi_after);
++				}
++			}
++		}
++		gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
++	}
+ 	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
+ 		for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
+ 			bitmap = i * adev->gfx.config.max_sh_per_se + j;
 diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
 index f17c3839aea1..a561038f3f79 100644
 --- a/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -4509,7 +5202,7 @@ index 000000000000..d2c25e461bf7
 +#endif /* _AUTOSERVO_PARAM_H */
 diff --git a/drivers/ps5/hdmi.c b/drivers/ps5/hdmi.c
 new file mode 100644
-index 000000000000..1193d840f5d6
+index 000000000000..81cc3b99d7e2
 --- /dev/null
 +++ b/drivers/ps5/hdmi.c
 @@ -0,0 +1,1226 @@
@@ -5035,8 +5728,8 @@ index 000000000000..1193d840f5d6
 +
 +void hdmiSystemResume(void)
 +{
-+	sceSetBackToUnpluggedSequence();
-+	sceSetBackToWaitResolutionSequence();
++	// sceSetBackToUnpluggedSequence();
++	// sceSetBackToWaitResolutionSequence();
 +	if (hdmi_ic_type == HDMI_IC_TYPE_FLAVA3) {
 +		i2c_cmd_4_2();
 +		// sceSetHdcpSequence1st();
@@ -6235,10 +6928,10 @@ index 000000000000..4af890c842a7
 +MODULE_LICENSE("GPL");
 diff --git a/drivers/ps5/spcie.c b/drivers/ps5/spcie.c
 new file mode 100644
-index 000000000000..8a073f2f0f0a
+index 000000000000..13337f7a0db9
 --- /dev/null
 +++ b/drivers/ps5/spcie.c
-@@ -0,0 +1,1084 @@
+@@ -0,0 +1,1120 @@
 +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
 +
 +#include <linux/module.h>
@@ -6648,6 +7341,42 @@ index 000000000000..8a073f2f0f0a
 +}
 +EXPORT_SYMBOL(icc_thermal_enable_notification);
 +
++int icc_device_power_control(u8 device, u8 state)
++{
++	u8 buf[ICC_MSG_MAX_SIZE] = {};
++	struct icc_msg *msg = (struct icc_msg *)buf;
++
++	msg->service_id = ICC_SERVICE_ID_DEVICE;
++	msg->msg_type = 0;
++	msg->length = 0x20;
++	msg->data[0] = device;
++	msg->data[1] = state;
++
++	return icc_query(buf, buf);
++}
++EXPORT_SYMBOL(icc_device_power_control);
++
++int icc_device_power_get(u8 device, u8 *state)
++{
++	u8 buf[ICC_MSG_MAX_SIZE] = {};
++	struct icc_msg *msg = (struct icc_msg *)buf;
++	int ret;
++
++	msg->service_id = ICC_SERVICE_ID_DEVICE;
++	msg->msg_type = 1;
++	msg->length = 0x20;
++	msg->data[0] = device;
++
++	ret = icc_query(buf, buf);
++	if (ret)
++		return ret;
++
++	*state = msg->data[2];
++
++	return 0;
++}
++EXPORT_SYMBOL(icc_device_power_get);
++
 +int icc_indicator_set_led(const u8 setting[], size_t setting_size)
 +{
 +	u8 buf[ICC_MSG_MAX_SIZE] = {};
@@ -7648,10 +8377,10 @@ index 2eedf44e6801..2785a47665be 100644
  extern void dmi_setup(void);
 diff --git a/include/linux/ps5.h b/include/linux/ps5.h
 new file mode 100644
-index 000000000000..7ed7adc99719
+index 000000000000..ed03edcab7c5
 --- /dev/null
 +++ b/include/linux/ps5.h
-@@ -0,0 +1,89 @@
+@@ -0,0 +1,92 @@
 +#ifndef _LINUX_PS5_H
 +#define _LINUX_PS5_H
 +
@@ -7678,18 +8407,18 @@ index 000000000000..7ed7adc99719
 +	ICC_SERVICE_ID_NVS		= 0x03,
 +	ICC_SERVICE_ID_POWER		= 0x04,
 +	ICC_SERVICE_ID_DEVICE		= 0x05,
-+	ICC_SERVICE_ID_UNKNOWN1		= 0x07,
++	ICC_SERVICE_ID_UNKNOWN_07	= 0x07,
 +	ICC_SERVICE_ID_BUTTON		= 0x08,
 +	ICC_SERVICE_ID_INDICATOR	= 0x09,
 +	ICC_SERVICE_ID_FAN		= 0x0a,
 +	ICC_SERVICE_ID_THERMAL		= 0x0b,
 +	ICC_SERVICE_ID_HDMI		= 0x10,
 +	ICC_SERVICE_ID_USBC		= 0x12,
-+	ICC_SERVICE_ID_UNKNOWN3		= 0x13,
++	ICC_SERVICE_ID_UNKNOWN_13	= 0x13,
 +	ICC_SERVICE_ID_CRASH_REPORT	= 0x14,
 +	ICC_SERVICE_ID_BDDRIVE		= 0x15,
-+	ICC_SERVICE_ID_UNKNOWN4		= 0x8c,
-+	ICC_SERVICE_ID_UNKNOWN5		= 0x8d,
++	ICC_SERVICE_ID_UNKNOWN_8C	= 0x8c,
++	ICC_SERVICE_ID_UNKNOWN_8D	= 0x8d,
 +	ICC_SERVICE_ID_SC_CONFIG	= 0x8e,
 +	ICC_SERVICE_ID_FLOYD		= 0x9a,
 +};
@@ -7728,6 +8457,9 @@ index 000000000000..7ed7adc99719
 +int icc_button_enable_all_notifications(u8 enable);
 +int icc_thermal_enable_notification(u8 enable);
 +
++int icc_device_power_control(u8 device, u8 state);
++int icc_device_power_get(u8 device, u8 *state);
++
 +int icc_indicator_set_led(const u8 setting[], size_t setting_size);
 +int icc_indicator_set_led_white(u8 level);
 +