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Author SHA1 Message Date
rmux
dc1a568126 x86/cpu/amd: set Oberon CPU model name (family 0x17, model 0x46) (#29) 2026-07-08 13:15:00 +02:00

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@@ -106,6 +106,21 @@ index dafbf581c515..791687363cbf 100644
X86_NR_SUBARCHS,
};
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 31f01e9c7114..ec3c32893cca 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -1163,6 +1163,10 @@ static void init_amd(struct cpuinfo_x86 *c)
/* AMD CPUs don't need fencing after x2APIC/TSC_DEADLINE MSR writes. */
clear_cpu_cap(c, X86_FEATURE_APIC_MSRS_FENCE);
+ if (c->x86 == 0x17 && c->x86_model == 0x46)
+ strscpy(c->x86_model_id, "AMD Custom Zen 2 (Oberon)",
+ sizeof(c->x86_model_id));
+
/* Enable Translation Cache Extension */
if (cpu_has(c, X86_FEATURE_TCE))
msr_set_bit(MSR_EFER, _EFER_TCE);
diff --git a/arch/x86/kernel/head64.c b/arch/x86/kernel/head64.c
index fd28b53dbac5..569fc764d267 100644
--- a/arch/x86/kernel/head64.c